Field effect transistors (FETs) that are utilized in semiconductor dies including logic circuits, such as high performance logic circuits, typically require low gate resistance, which can be achieved by utilizing silicided polysilicon gates or metal gates. For logic circuits, it is desirable to integrate FETs with polysilicon devices, such as polysilicon resistors and fuses, on a common substrate. However, the integration of metal gates with polysilicon resistors and fuses on a common substrate in a conventional process flow can require a number of additional masking steps, which can undesirably increase fabrication cost.
As a result of continuing advances in technology, the feature size of FETs utilized in logic circuits, such as high performance logic circuits, continues to scale down, which advantageously enables a corresponding reduction in the size of the semiconductor die on which the logic circuit is fabricated. However, as FET feature size is scaled down, separation between gate and source/drain contacts is also decreased. As a result, it can become increasingly difficult to ensure sufficient separation between the gate and source/drain contacts so as to avoid gate-to-source/drain contact shorts.
In a conventional process flow, the source/drain contacts can be aligned to the gates of FETs utilized in logic circuits, such as high performance logic circuits, by aligning a contact mask to a gate pattern. However, as the FETs are scaled down in size, lithographic misalignment tolerance associated with contact mask-to-gate mask alignment can be correspondingly reduced. As a result, the conventional process flow can cause increased gate-to-source/drain contact shorts as FETs are scaled down in size, thereby undesirably reducing manufacturing yield.